This time we'll take a quick look at another hybrid - Cswitch 'Configurable Switch Array' (this company is unfortunately defunct at this moment and looking for buyer).
This mutant can be viewed as a Network Processor (NP) with eFPGA. Or, it may as well be classified as FPGA with deadly dose of hardware mega-blocks aimed at packet processing and networking applications.
Since it's got sizable genome from both NP and FPGA, let's call it NPGA! So, the Cswitch twisted personality includes:
1) Fixed, high-speed (2 GHz), top-level interconnect in the form of any-to-any cross-connect switch. Not an FPGA thing. Found in some NPs.
2) Flexible, highly-configurable, multi-standard I/O that covers the gamut of single-ended, differential and terminated options. This I/O sports built-in flops (SDR and DDR), FIFOs, DLLs and ECC logic (!!!). Not found in NP. Taken from FPGA, but enriched and expanded.
3) An assortment of configurable, global and local clocks, with PLLs, dividers, skew management and clock gating elements. Again, not found in NP, typical of FPGA, except that these clocks can entertain 2GHz (!)
4) One Configurable Packet Processor engine. Consists of programmable Packet Parser, Reconfigurable Arithmetic Unit and Reconfigurable(!) CAM block. Not found in FPGA. Typical of NP, with caveat that Cswitch's packet engine is more configurable.
5) Handful of fast (1Gbps/pin), multi-standard controllers for external memories (DDR1/2, QDR1/2, RLDRAM1/2). Typical of NP. Also found in FPGA, but Cswitch wins on speed, variety and number of available memory controllers.
6) Few dozen SerDes with MACs, including 10GE and PCIe. NP normally does not have this many SerDes, while high-end FPGA may have comparable number of them, but far fewer MAC blocks, if at all.
7) Thousands of Programmable Logic Blocks (at 500MHz) with hundreds of both fine and course-grained, single and dual-port Memory Blocks at incredible 1GHz (!), some with built-in FIFO controller. Typical for FPGA. Not found at all in NP. FPGA normally possesses more logic and memory blocks than this, but cannot entertain the Cswitch speeds.
8) Cswitch design flow is hardware/FPGA-centric, with RTL and synthesis acting as the main implementation vehicle and C compiler/debugger for the Packet Processor engine (NP flow) standing on the side. The compiled C binary is merged with main flow via an HDL wrapper.
This NPGA guy from Cswitch is quite a character, isn't it, esp. knowing that it is carved out of the aging 90nm stock.
Stay tuned for another recent FPGA-ish mutant with similarly strong personality...
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