eFPGA - Another Fusion in the Works!

We touched on AMD-pioneered fusion of GPU to CPU in the previous article and wondered if the desktop processors would also embrace some kind of programmable-ity at the gate level, to so complement the healthy C-to-Hardware movements in the compiler space and allow for dynamic, application-driven processor customizations.

Well, this new fusion, 'Gate Fusion' is reaching the critical mass!

It is the French side of the Atlantic that accelerated the particles this time, where Menta (www.menta.fr) developed embedded FPGA - eFPGA cores in the form of soft IP. Chip companies would then buy Menta's eFPGA core of desired size and integrate it on their design to so get the live capability to add/change logic. Important to note is the soft IP attribute of the Menta eFPGA, which opens it to wider foundry access and offers portability across process technology! Another French company, M2000, was also innovating in the eFPGA space (until they recently became Abound Logic, changed focus, and moved to US).

Simply put, eFPGA is about embedding some uncommitted field-programmable gates in an otherwise ASSP silicon, such as general-purpose processor. Main difference between an FPGA-with-embeddedCPU and CPU-with-eFPGA is in the ratio of the two -- While former is primarily an FPGA (with some CPU), the latter is primarily a CPU (with some FPGA). Moreover, just like embedded Flash or embedded DRAM, eFPGA core(s) can be integrated in any kind of ASSP, not only the CPU, and for reasons more mundane than acceleration through instruction set extension (think 'bug deflection' and 'future-proofing' here).

Tensilica Xtensa product line has been riding the 'custom processor' wave for quite some time, offering rather automated acceleration of its instruction set. The key with Tensilica was however that the application code had to be written and analyzed before processor was manufactured. The bottlenecks are hence identified a-priori and addressed in pre-production, that is in hard gates. ARC Configurable Cores fall into the same category.

The problem in either case is that, should application change enough, the hard-wired accelerator could easily become less of an asset and more of a burden. That's where the eFPGA comes to rescue as its customer-visible gates are soft, that is field-reprogrammable.

Stretch S6000 family is an interesting marriage of the best from both worlds and probably the first CPU with embedded FPGA. 'Stretch' is marketed under the catchy 'Software Configurable Processor' banner. It contains VLIW Xtensa processing core with Tensilica 'Instruction Set Extension Fabric', further augmented by Menta eFPGA-based 'Programmable Accelerator'. Higher-end versions of the 'Stretch' also contain 'Processor Array' interface, which is to allow connecting multiple 'Stretch' units into some kind of networking topology, for scalability stretch.

It seems to us that pure-play FPGA is the thing of the past -- As the programmable imperative is gaining momentum, standard parts are being enriched with eFPGA cores, while true FPGAs are doped with heavy doses of complex hard IP and morphing into eFPGA-like parts.

This Fusion both consolidates and diversifies -- The technologies that are traditionally thought of as distinct and unique are now fused on the common die, which isn't merely integration and density scaling. Yet, the variety of target applications, coupled with acute energy crisis and cry for doing the most on the least, increase the diversity of the so 'fused' chips by calling for differences in the ratios of the packaged content.

This Fusion is an unstoppable, chain reaction and occurring at multiple levels -- We are yet to touch on its mixed-signal and RF aspects...